Yosys Open SYnthesis Suite, including Verilog synthesizer
Yosys is a framework for Verilog RTL synthesis. It currently has
extensive Verilog-2005 support and provides a basic set of synthesis
algorithms for various application domains.
Version: 0.40
See also: yosys-devel.
General Commands | |
| yosys | Yosys Open SYnthesis Suite |
| yosys-filterlib | Yosys Open SYnthesis Suite Filterlib |
| yosys-smtbmc | write design to SMT2-LIBv2 file |