A fast simulator for synthesizable Verilog
https://veripool.org/verilator/
Verilator is the fastest free Verilog HDL simulator. It compiles
synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis
assertions into C++ or SystemC code. It is designed for large projects
where fast simulation performance is of primary concern, and is
especially well suited to create executable models of CPUs for
embedded software design teams.
Version: 5.024
General Commands | |
| verilator | Translate and simulate SystemVerilog code using C++/SystemC |
| verilator_coverage | Verilator coverage analyzer |
| verilator_gantt | manual page for verilator_gantt - |
| verilator_profcfunc | manual page for verilator_profcfunc - |