Package “ASIM/LIP6” has 39 man pages.

genlib.1alc(1)

genlib is a set of C functions dedicated to procedural generation purposes. From a user point of view, genlib is a circuit's description language that allows...

genlib is a set of C functions dedicated to procedural generation purposes. From a user point of view, genlib is a circuit's description language that allows...

nero.1alc(1)

nero is a simple router suited for small academic designs. Currently it can process designs of size up to 4K gates.Global Routing A design is considered as big...

nero is a simple router suited for small academic designs. Currently it can process designs of size up to 4K gates.Global Routing A design is considered as big...

DPGEN_AND2.3alc(3)

Generate a N bits two inputs AND with an output power of drive named modelname. Valid drive are : 2 or 4.Terminal NamesBehavior

Generate a N bits two inputs AND with an output power of drive named modelname. Valid drive are : 2 or 4.Terminal NamesBehavior

DPGEN_AND3.3alc(3)

Generate a N bits three inputs AND with an output power of drive named modelname. Valid drive are : 2 or 4.Terminal NamesBehavior

Generate a N bits three inputs AND with an output power of drive named modelname. Valid drive are : 2 or 4.Terminal NamesBehavior

DPGEN_AND4.3alc(3)

Generate a N bits four inputs AND with an output power of drive named modelname. Valid drive are : 2 or 4.Terminal NamesBehavior

Generate a N bits four inputs AND with an output power of drive named modelname. Valid drive are : 2 or 4.Terminal NamesBehavior

DPGEN_BUFF.3alc(3)

Generate a N bits buffer with an output power of drive named modelname. Valid drive are : 2, 3 or 4.Terminal NamesBehavior

Generate a N bits buffer with an output power of drive named modelname. Valid drive are : 2, 3 or 4.Terminal NamesBehavior

DPGEN_BUSE.3alc(3)

Generate a N bits two inputs tristate with named modelname.Terminal NamesBehavior

Generate a N bits two inputs tristate with named modelname.Terminal NamesBehavior

DPGEN_DFF.3alc(3)

Generate a N bits dynamic flip-flop named modelname. The two latches of this flip-flop are dynamic, i.e. the data is stored in a capacitor.

Generate a N bits dynamic flip-flop named modelname. The two latches of this flip-flop are dynamic, i.e. the data is stored in a capacitor.

DPGEN_DFFT.3alc(3)

Generate a N bits dynamic flip-flop with scan-path named modelname. The two latches of this flip-flop are dynamic, i.e. the data is stored in a capacitor.

Generate a N bits dynamic flip-flop with scan-path named modelname. The two latches of this flip-flop are dynamic, i.e. the data is stored in a capacitor.

DPGEN_INV.3alc(3)

Generate a N bits inverter with an output power of drive named modelname. Valid drive are : 1, 2, 3 or 4.Terminal NamesBehavior

Generate a N bits inverter with an output power of drive named modelname. Valid drive are : 1, 2, 3 or 4.Terminal NamesBehavior

DPGEN_MUX2.3alc(3)

Generate a N bits two inputs multiplexer with named modelname. Valid drive are : 1, 2 or 4.Terminal NamesBehavior

Generate a N bits two inputs multiplexer with named modelname. Valid drive are : 1, 2 or 4.Terminal NamesBehavior

DPGEN_NAND2.3alc(3)

Generate a N bits two inputs NAND with an output power of drive named modelname. Valid drive are : 1 or 4.Terminal NamesBehavior

Generate a N bits two inputs NAND with an output power of drive named modelname. Valid drive are : 1 or 4.Terminal NamesBehavior

DPGEN_NAND3.3alc(3)

Generate a N bits three inputs NAND with an output power of drive named modelname. Valid drive are : 1 or 4.Terminal NamesBehavior

Generate a N bits three inputs NAND with an output power of drive named modelname. Valid drive are : 1 or 4.Terminal NamesBehavior

DPGEN_NAND4.3alc(3)

Generate a N bits four inputs NAND with an output power of drive named modelname. Valid drive are : 1 or 4.Terminal NamesBehavior

Generate a N bits four inputs NAND with an output power of drive named modelname. Valid drive are : 1 or 4.Terminal NamesBehavior

DPGEN_NBUSE.3alc(3)

Generate a N bits two inputs tristate with a complemented output named modelname.Terminal NamesBehavior

Generate a N bits two inputs tristate with a complemented output named modelname.Terminal NamesBehavior

DPGEN_NMUX2.3alc(3)

Generate a N bits two inputs multiplexer with a complemented output and a power of drive named modelname. Valid drive are : 2 or 4.Terminal NamesBehavior

Generate a N bits two inputs multiplexer with a complemented output and a power of drive named modelname. Valid drive are : 2 or 4.Terminal NamesBehavior

DPGEN_NOR2.3alc(3)

Generate a N bits two inputs NOR with an output power of drive named modelname. Valid drive are : 1 or 4.Terminal NamesBehavior

Generate a N bits two inputs NOR with an output power of drive named modelname. Valid drive are : 1 or 4.Terminal NamesBehavior

DPGEN_NOR3.3alc(3)

Generate a N bits three inputs NOR with an output power of drive named modelname. Valid drive are : 1 or 4.Terminal NamesBehavior

Generate a N bits three inputs NOR with an output power of drive named modelname. Valid drive are : 1 or 4.Terminal NamesBehavior

DPGEN_NOR4.3alc(3)

Generate a N bits four inputs NOR with an output power of drive named modelname. Valid drive are : 1 or 4.Terminal NamesBehavior

Generate a N bits four inputs NOR with an output power of drive named modelname. Valid drive are : 1 or 4.Terminal NamesBehavior

DPGEN_OR2.3alc(3)

Generate a N bits two inputs OR with an output power of drive named modelname. Valid drive are : 2 or 4.Terminal NamesBehavior

Generate a N bits two inputs OR with an output power of drive named modelname. Valid drive are : 2 or 4.Terminal NamesBehavior

DPGEN_OR3.3alc(3)

Generate a N bits three inputs OR with an output power of drive named modelname. Valid drive are : 2 or 4.Terminal NamesBehavior

Generate a N bits three inputs OR with an output power of drive named modelname. Valid drive are : 2 or 4.Terminal NamesBehavior

DPGEN_OR4.3alc(3)

Generate a N bits four inputs OR with an output power of drive named modelname. Valid drive are : 2 or 4.Terminal NamesBehavior

Generate a N bits four inputs OR with an output power of drive named modelname. Valid drive are : 2 or 4.Terminal NamesBehavior

DPGEN_RF1.3alc(3)

Generate a register file of regNumber words of N bits whitout decoder named modelname. The DPGEN_RF1R0 variant differs from the DPGEN_RF1 in that the register...

Generate a register file of regNumber words of N bits whitout decoder named modelname. The DPGEN_RF1R0 variant differs from the DPGEN_RF1 in that the register...

DPGEN_RF1D.3alc(3)

Generate a register file of regNumber words of N bits with decoder named modelname. The DPGEN_RF1DR0 variant differs from the DPGEN_RF1D in that the register of...

Generate a register file of regNumber words of N bits with decoder named modelname. The DPGEN_RF1DR0 variant differs from the DPGEN_RF1D in that the register of...

DPGEN_SFF.3alc(3)

Generate a N bits static flip-flop named modelname. The two latches of this flip-flop are static, i.e. each one is made of two interters looped togethers.

Generate a N bits static flip-flop named modelname. The two latches of this flip-flop are static, i.e. each one is made of two interters looped togethers.

DPGEN_SFFT.3alc(3)

Generate a N bits static flip-flop with scan-path named modelname. The two latches of this flip-flop are i.e. each one is made of two interters looped...

Generate a N bits static flip-flop with scan-path named modelname. The two latches of this flip-flop are i.e. each one is made of two interters looped...

DPGEN_XNOR2.3alc(3)

Generate a N bits two inputs exclusive NOR with an output power of drive named modelname. Valid drive are : 1 or 4.Terminal NamesBehavior

Generate a N bits two inputs exclusive NOR with an output power of drive named modelname. Valid drive are : 1 or 4.Terminal NamesBehavior

DPGEN_XOR2.3alc(3)

Generate a N bits two inputs exclusive OR with an output power of drive named modelname. Valid drive are : 1 or 4.Terminal NamesBehavior

Generate a N bits two inputs exclusive OR with an output power of drive named modelname. Valid drive are : 1 or 4.Terminal NamesBehavior

GENLIB_MACRO.3alc(3)

The GENLIB_MACRO() fonction call is the generic interface to all genlib macro generators. As all generators do not have the sames arguments it takes a variable...

The GENLIB_MACRO() fonction call is the generic interface to all genlib macro generators. As all generators do not have the sames arguments it takes a variable...