Package alliance

VLSI EDA System

https://soc-extras.lip6.fr/en/alliance-abstract-en/

Alliance is a complete set of free cad tools and portable libraries for VLSI
design. It includes a vhdl compiler and simulator, logic synthesis tools,
and automatic place and route tools. A complete set of portable cmos libraries
is provided. Alliance is the result of a twelve year effort spent at SoC
department of LIP6 laboratory of the Pierre & Marie Curie University (Paris
VI, France). Alliance has been used for research projects such as the 875 000
transistors StaCS superscalar microprocessor and 400 000 transistors ieee
Gigabit HSL Router.

Alliance provides CAD tools covering most of all the digital design flow:

 * VHDL Compilation and Simulation
 * Model checking and formal proof
 * RTL and Logic synthesis
 * Data-Path compilation
 * Macro-cells generation
 * Place and route
 * Layout edition
 * Netlist extraction and verification
 * Design rules checking

Alliance is listed among Fedora Electronic Lab (FEL) packages.
General Commands (Section 1)
abl.1alc
libablmmm.a is a library that enables to represent a boolean function in a LISP-like form. An ABL is a prefixed internal representation for a boolean function...
alcbanner.1alc
alcbanner display on stdout a standardized banner for the Alliance tools. This is a compiled version of the alliancebanner(2) function.
alc_bug_report.1alc
This tool is under development at the ASIM department of the LIP6 laboratory. We need your feedback to improve documentation and tools.
alc_origin.1alc
This software belongs to the ALLIANCE CAD SYSTEM developed by the ASIM team at LIP6 laboratory of Université Pierre et Marie CURIE, in Paris, France. Web ...
asimut.1alc
asimut is a logical simulation tool for hardware descriptions. It compiles and loads a complete hardware description written in VHDL (Very high speed integrated...
aut.1alc
aut is a set of utilities functions and types that may be useful.
bdd.1alc
bdd is a library that enables to represent a boolean expression as a Multi Reduced Ordered Binary Decision Diagrams.
boog.1alc
boog is a mapper of a behavioural description onto a predefined standard cell library as SXLIB. It is the second step of the logic synthesis: it builds a gate...
boom.1alc
BOOM is used for the first step of the synthesis process. It optimizes a behavioural description using a Reduced Ordered Binary Decision Diagram representation...
cougar.1alc
Lynx changed its name to Cougar during May 2002 in order to avoid name conflict with the famous text-mode Web browser. Cougar is a hierarchical layout...
dreal.1alc
Dreal is a hierarchical real layout viewer. All functionnalities can be accessed through different menus. Dreal works under Motif and X11r5. When entering...
druc.1alc
DRuC is a general parametrized VLSI design rule checker. This tool replace the VERSATIL tool that is not anymore supported. This manual presents the layout...
exp.1alc
Input is an ascii format file including numeric expessions with variables. Input file can includes other input files thanks to an inclusion directive. exp reads...
flatbeh.1alc
flatbeh synthetize a VHDL behavioral data-flow description from a structural description. It flattens the structural description (it can be a hierarchy of macro...
flatlo.1alc
flatlo FLATen LOgical figure flatlo logical_figure instance output_name flattens "instance" in "logical_figure" flatlo -r logical_figure output_name flattens...
flatph.1alc
flatph FLATen PHysical figure
fmi.1alc
Made to run on FSM descriptions, fmi supports the same subset of VHDL as syf (for further information about this subset see SYF(1) and FSM(5)). fmi uses a...
fsm.1alc
fsm is a library that enables to represent finite state machine.
fsp.1alc
Made to run on FSM descriptions, fsp supports the same subset of VHDL as syf (for further information about this subset see SYF(1) and FSM(5)). fsp uses a...
genlib.1alc
genlib is a set of C functions dedicated to procedural generation purposes. From a user point of view, genlib is a circuit's description language that allows...
genpat.1alc
Genpat is a set of C fonctions that allows a procedural description of input pattern file for the logic simulator ASIMUT. The Unix genpat command accepts a C...
graal.1alc
Graal is a hierarchical symbolic layout editor. All functionnalities can be accessed through different menus. Among them exists a design rule checker performing...
k2f.1alc
k2f is a FSM translator from ALLIANCE format (".fsm") to Berkeley format (".kiss2").
l2p.1alc
Two main kind of cells can be used as inputs for l2p : First, you can use l2p to print symbolic layout cells. File formats can be .ap or .cp . This is given by...
log.1alc
log is a set of structures and functions that permits to manipulate several representations of boolean functions. Several programs and libraries of the cao-vlsi...
loon.1alc
loon is a CAD tool that allows to remove fanout problems within a gate netlist and also to optimize the delay. The netlist can be hierarchical and is flattened...
lvx.1alc
lvx compares two gate-level or block level net-list. The goal is to compare a specification net-list (logical net-list), the input to a place and route tool...
m2e.1alc
No description.
MBK_CATA_LIB.1alc
MBK_CATA_LIB sets the directories that are to be searched thru for reading. When instantiating a cell for example, the first cell that is found with the given...
MBK_CATAL_NAME.1alc
MBK_CATAL_NAME sets the name of the catalog file, that contains information about the cells of a design. The catalog file syntax is a cellname, plus a flag. The...
MBK_CK.1alc
MBK_CK sets the pattern to be matched in a name to indicate a clock for the tools based upon mbk. Its default value is ck. Therefore all names of the form...
MBK_FILTER_SFX.1alc
MBK_FILTER_SFX tells to Alliance the extention set by compression tools. This variable must be set in order to activate filters. Note the leading points of...
MBK_IN_FILTER.1alc
MBK_IN_FILTER set the input filter for reading compressed Alliance files. Filter is typically a string containing filename and options. This filter must read...
MBK_IN_LO.1alc
MBK_IN_LO sets the logical input format of the mbk database. The database will be filled with information found in the given format file.
MBK_IN_PH.1alc
MBK_IN_PH sets the physical input format of the mbk data structure. The data structure will be filled with information found in the given format file.
MBK_OUT_FILTER.1alc
MBK_OUT_FILTER sets the output filter for writing compressed Alliance files. Filter is typically a string containing filename and options. This filter must read...
MBK_OUT_LO.1alc
MBK_OUT_LO sets the logical output format of the mbk data structure. The files resulting of the work on mbk will have the given format.
MBK_OUT_PH.1alc
MBK_OUT_PH sets the physical output format of the mbk data structure. The files resulting of the work on mbk will have the given format.
MBK_SEPAR.1alc
MBK_SEPAR sets the character that is to be used while concatening names, during a flatten, for example.
MBK_TRACE_GETENV.1alc
If MBK_TRACE_GETENV is set to "yes", all alliance tools will print debug info to stdout each time a getenv() syscall is done.
MBK_VDD.1alc
MBK_VDD sets the pattern to be matched in a name to indicate a power supply for the tools based upon mbk. Its default value is vdd. Therefore all names of the...
MBK_VSS.1alc
MBK_VSS sets the pattern to be matched in a name to indicate a ground node for the tools based upon Its default value is vss. Therefore all names of the form...
MBK_WORK_LIB.1alc
MBK_WORK_LIB sets the directory where are saved the results of an invocation of mbk or genlib. This directory is considered to be, from an mbk point of view...
moka.1alc
moka is a CTL model checker. Made to run on FSM or RTL descriptions, moka supports the same VHDL subset as syf or boom (for further informations about this...
nero.1alc
nero is a simple router suited for small academic designs. Currently it can process designs of size up to 4K gates.Global Routing A design is considered as big...
ocp.1alc
ocp is an automatic place tool for standard-cells. input net-list The netlist file describes the input net-list. ocp supports a hierarchical net-list. In this...
pat2spi.1alc
pat2spi is a translator from ALLIANCE pattern format (".pat") to spice PWL format (".spi"). An optional slope parameter can be used to specify the slope value...
proof.1alc
Made to run on a data-flow description, proof supports the same subset of VHDL as asimut and boom and boog (for further informations about this subset, please...
ring.1alc
source defines two input files: -- the file describing the input netlist (MBK_IN_LO(1) format). example: source.al -- the parameter file: source.rin This file...
s2r.1alc
The goal of s2r is to perform the translation from the symbolic layout to physical layout for the foundry. s2r uses a technolgy file whose name is defined by...
scapin.1alc
SCAPIN is an automatic scan path generator for gate level netlists. SCAPIN inserts a scan path in the netlist Input_name and drives a new netlist Output_name...
syf.1alc
syf is a Finite State Machine synthesizer. syf allows a fast generation of VHDL Data Flow description (see vbe(5)) from a VHDL Finite State Machine description...
vasy.1alc
VASY is a hierarchical VHDL Analyzer for Synthesis. VASY performs a semantic analysis of a VHDL RTL description filename, with a VHDL subset much more extended...
x2y.1alc
x2y is a netlist format converter al ALLIANCE netlist ap ALLIANCE layout cct HILO netlist cp VTI layout edi EDIF netlist or layout fne VTI extracted netlist hns...
xpat.1alc
Xpat is a pattern viewer. All functionnalities can be accessed through different menus. Xpat works under Motif and X11r6. When entering Xpat, the main window...
xsch.1alc
Xsch is a graphical schematic viewer. All functionnalities can be accessed through different menus. Xsch works under Motif and X11r6. When entering Xsch, the...