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Package alliance



Alliance is a complete set of free cad tools and portable libraries for VLSI
design. It includes a vhdl compiler and simulator, logic synthesis tools,
and automatic place and route tools. A complete set of portable cmos libraries
is provided. Alliance is the result of a twelve year effort spent at SoC
department of LIP6 laboratory of the Pierre & Marie Curie University (Paris
VI, France). Alliance has been used for research projects such as the 875 000
transistors StaCS superscalar microprocessor and 400 000 transistors ieee
Gigabit HSL Router.

Alliance provides CAD tools covering most of all the digital design flow:

 * VHDL Compilation and Simulation
 * Model checking and formal proof
 * RTL and Logic synthesis
 * Data-Path compilation
 * Macro-cells generation
 * Place and route
 * Layout edition
 * Netlist extraction and verification
 * Design rules checking

Alliance is listed among Fedora Electronic Lab (FEL) packages.

Version: 5.1.1

See also: alliance-devel, alliance-libs.

General Commands

MBK_CATAL_NAME.1alc define the mbk catalog file
MBK_CATA_LIB.1alc define the mbk catalog directory
MBK_CK.1alc define the clock name pattern
MBK_FILTER_SFX.1alc define the inputoutput filter suffixe.
MBK_IN_FILTER.1alc define the input filter
MBK_IN_LO.1alc define the logical input format of mbk and genlib
MBK_IN_PH.1alc define the physical input format of mbk and genlib
MBK_OUT_FILTER.1alc define the input filter
MBK_OUT_LO.1alc define the logical output format of mbk and genlib
MBK_OUT_PH.1alc define the physical output format of mbk and genlib
MBK_SEPAR.1alc define the separator character for hierarchy
MBK_TRACE_GETENV.1alc defines getenv() debug output
MBK_VDD.1alc define the high level power name pattern
MBK_VSS.1alc define the ground power name pattern
MBK_WORK_LIB.1alc define the mbk working directory
abl.1alc Prefixed representation for boolean functions
alcbanner.1alc Display a standardized banner for Alliance tools
asimut.1alc A simulation tool for hardware descriptions
aut.1alc Memory allocation, and hash tables management
bdd.1alc Mutli Reduced Ordered Binary Decision Diagrams
boog.1alc Binding and Optimizing On Gates.
boom.1alc BOOlean Minimization
cougar.1alc Hierarchical netlist extractor
dreal.1alc Graphic real layout viewer
druc.1alc Design Rule Checker
exp.1alc Input is an ascii format file including numeric expessions with variables. Input file can includes other input files thanks to an inclusion directive.
flatbeh.1alc Synthetize a behavioral description from a structural description
flatlo.1alc FLATen LOgical figure
flatph.1alc FLATen PHysical figure
fmi.1alc FSM state miminization
fsm.1alc Finite State Machine representation.
fsp.1alc Formal proof between two FSM descriptions
genlib.1alc Procedural design language based upon C.
genpat.1alc genpat, A procedural pattern file generator
graal.1alc symbolic layout editor
k2f.1alc k2f, FSM translator ALLIANCE format from/to Berkeley format
l2p.1alc l2p- Creates a PostScript file from a symbolic layout file,or from a physical layout file.
log.1alc logical representations for boolean functions and utilities.
loon.1alc Local optimizations of Nets.
lvx.1alc Logical Versus eXtracted net-list comparator
moka.1alc Model checker ancestor
nero.1alc Negotiating Router
ocp.1alc Standard Cell Placer
pat2spi.1alc pat2spi, PAT ALLIANCE format translator to Spice PWL format
proof.1alc Formal proof between two behavioural descriptions
ring.1alc PAD RING router
s2r.1alc s2r- Process mapping from symbolic layout to physical layout
scapin.1alc Scan path insertion
syf.1alc Finite State Machine synthesizer.
vasy.1alc VHDL Analyzer for Synthesis
x2y.1alc Netlist Format converter
xpat.1alc graphic pattern viewer
xsch.1alc graphical schematic viewer