vhdl.5alc man page

ALLIANCE VHDL Subset

Description

The ALLIANCE VHDL subset is dedicated to digital synchronous circuits design. The same subset is used for:

logic simulation (asimut)
logic synthesis (boom, boog, loon)
functionnal abstraction (yagle)
formal proof (proof)

The ALLIANCE VHDL subset is fully compatible with the IEEE VHDL standard Ref. 1076 (1987). That means that a VHDL description using the ALLIANCE subset can be simulated with any full-VHDL commercial compiler-simulator.

Here follows the main restrictions of the ALLIANCE subset.

The VHDL description of a circuit is made of two separate parts: the external view and the internal view.

The external view defines the name of the circuit and its interface. The interface of a circuit is a list of ports. Each port is specified by its name, its mode, its type, its constraint for an array and, its kind.

The mode of a port depends only on the manner the port is used inside the circuit (in the internal view of the circuit). If the value of a port is to be read in the view of the description, the port must be declared with the mode in. If the value of a port is to be written by the internal view, the port must be declared with the mode out. If both above conditions are satisfied the port must be declared with the mode inout.

Only structural and behavioural data flow are supported as internal view.

In order to allow automatic translation from structural VHDL to other netlist formats (EDIF, ALLIANCE, COMPASS, ...) it is not possible to mix behavioural and structural description. Of course, a circuit, a subcircuit or a cell can have two different descriptions:

a structural view may be defined in a file with a .vst extension (see vst(5)).
a behavioural data flow description may be defined in a file with a .vbe extension (see vbe(5)).

A typical VHDL model will be made of a hierarcical structural description (a hierarchy of structural files) and, for each leaf cell, a behavioural description.

In a behavioural description, only concurrent statements (except process) are supported. Up to now, sequential statements are not allowed by the ALLIANCE VHDL compiler.

Timing information can be specified in behavioural descriptions using After clauses. However, those delays are currently only used for simulation. After clauses are supported but not used for synthesis and formal proof.

A predefined set of types has been defined (other user defined types are not supported):

bit

the predefined standard bit type ('0' or '1')

bit_vector

array of bit

mux_bit

a resolved subtype of bit using the mux resolution function. This function checks that only one driver is actually connected to a signal. The effective value of the signal is the value of the active driver. If all drivers are disconnected, the value of the signal is '1' (pull up). A signal of type mux_bit must be declared with the kind bus.

mux_vector

array of mux_bit

wor_bit

a resolved subtype of bit using the wor resolution function. This function allows a signal be driven by more than one driver. All active drivers have to drive the same value. The effective value of the signal is the value of active drivers. If all drivers are disconnected, the value of the signal is '1' (pull up). A signal of type wor_bit must be declared with the kind bus.

wor_vector

array of wor_bit

reg_bit

a resolved subtype of bit using the reg resolution function. This function checks that only one driver is actually connected to a signal. The effective value of the signal is the value of the active driver. A signal of type reg_bit must be declared with the kind register (which makes the signal keep its previous value when all drivers are disconnected).

reg_vector

array of reg_bit

In the next ALLIANCE release the VHDL subset will be largely extended (sequential statements, user defined types) .

See Also

vst(5), vbe(5), asimut(1), boom(1), loon(1), boog(1), proof(1)

Referenced By

asimut.1alc(1), boog.1alc(1), flatbeh.1alc(1), loon.1alc(1), proof.1alc(1), syf.1alc(1), vasy.1alc(1), vasy.5alc(5), vbe.5alc(5), vst.5alc(5).

October 1, 1997 VHDL subset of ASIM/LIP6/CAO-VLSI lab.