vrq man page

Vrq — manual page for Vrq 1.0.124,


vrq [options] <file1> [<file2>...]


'Vrq' is a framework for creating verilog based tools.


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Binary install path
Library install path
Plugin install path
Include install path
Compiler flags used
Linker flags used
Libraries used
Randomize heap
-y <directory>
Search directory for module definitions
-f <filename>
Read options from <filename>
-v <lib_filename>
Search file for module definitions
-l <filename>
Set log file to <filename>
-w <message>=<policy>
Set policy for warning <message> to <policy>; ignore, warning, error, info
-w all=<policy>
Set policy for all warnings to <policy>; ignore, warning, error, info
List all warning messages
Specify library suffix to <extension>
Enable System Verilog support
Dump internal tree
Print debug/statistics info
Print minimal runtime info

-lexbuffersize <bufferSize> Set lexer buffer size (default=1048576)

Infer reg and wire vectors
Best effort attempt to keep tick defines and `include statements in code (EXPERIMENTAL)
Do not allow undefined macros
-o <filename>
Specify output file
-dir <directory>
Specify output directory
-pragma <regexp>
Extended regular expression template for pragma comments
-passthru <name>
Pass through ifdef blocks with label
Specify include search path
Define `define
Define plusargs
-tool builder
Auto route hierarchy
-tool coverage
Add line coverage instrumentation
-tool dump
Print verilog output
-tool filter
Extract elements of hierarchy
-tool flatten
Reduce to single level hiearchy
-tool rectify
Replace all X constants with 0 or 1
-tool sim
Verilog simulator
-tool stats
Print summary of hiearchy
-tool xprop
Add X propagation instrumentation

* 'builder' Options

File extension for files to be expanded
Generate dependency info
Dump vebose log of actions

* 'coverage' Options

+coverage_output_file=<filename> Filename for coverage line mapping info

* 'dump' Options

Use alternate rxnor op ^~
Force part selects on all vectors
Convert all logical ops to vector ops
Convert all comments to c++ style
Split wire declaration assignments
Force begin/end block after event statement
Replace null statements with begin/end pairs
Add spaces around binary operators
Create explicit declarations for implicitly declared variables
strip out all attributes

+dump-timescale=<timescale> emit `timescale <timescale> statements for all modules missing `timescale declarations

Simplify constant expressions (EXPERIMENTAL)

* 'filter' Options

+filter-default-policy-keep keep all element by default

+filter-default-policy-delete delete all element by default (tool default behavior)

keep comment
delete comment
keep vrq comment
delete vrq comment
keep program pragma
delete program pragma
keep instance reference

+filter-instance-ref-delete delete instance reference

keep gate instance
delete gate instance
keep call to a task

+filter-task-enable-delete delete call to a task

keep call to enable a systask

+filter-systask-call-delete delete call to enable a systask

keep call to a timing task

+filter-timing-call-delete delete call to a timing task

+filter-function-call-keep keep call to a function

+filter-function-call-delete delete call to a function

keep reference to a enum
delete reference to a enum
keep reference to a type
delete reference to a type
keep net declaration
delete net declaration
keep variable declaration
delete variable declaration
keep parameter declaration
delete parameter declaration

+filter-specparam-decl-keep keep specify parameter declaration

+filter-specparam-decl-delete delete specify parameter declaration

keep port declaration
delete port declaration
keep genvar declaration

+filter-genvar-decl-delete delete genvar declaration

keep type declaration

+filter-typedef-decl-delete delete type declaration

keep initial block
delete initial block
keep always block
delete always block
keep always latch block

+filter-always-latch-delete delete always latch block

keep always flip-flop block
delete always flip-flop block
keep always combinational logic block

+filter-always-comb-delete delete always combinational logic block

keep specify block

+filter-specify-ref-delete delete specify block

keep procedural assignment
delete procedural assignment
keep generate intialize assignment
delete generate intialize assignment
keep procedural assignment with add
delete procedural assignment with add
keep procedural assignment with subtract
delete procedural assignment with subtract
keep procedural assignment with mul
delete procedural assignment with mul
keep procedural assignment with div
delete procedural assignment with div
keep procedural assignment with mod
delete procedural assignment with mod
keep procedural assignment with bitwise and
delete procedural assignment with bitwise and
keep procedural assignment with bitwise or
delete procedural assignment with bitwise or
keep procedural assignment with bitwise xor
delete procedural assignment with bitwise xor
keep procedural assignment with left shift
delete procedural assignment with left shift
keep procedural assignment with right shift
delete procedural assignment with right shift
keep procedural assignment with left arithmetic shift

+filter-lsha-assign-delete delete procedural assignment with left arithmetic shift

keep procedural assignment with right arithmetic shift

+filter-rsha-assign-delete delete procedural assignment with right arithmetic shift

keep force statement
delete force statement
keep release statement
delete release statement
keep nonblocking assignment
delete nonblocking assignment
keep if statement
delete if statement
keep forever statement
delete forever statement
keep repeat statement
delete repeat statement
keep while statement
delete while statement
keep wait statement
delete wait statement
keep for statement
delete for statement
keep case statement
delete case statement
keep casex statement
delete casex statement
keep casez statement
delete casez statement
keep continious assignment
delete continious assignment
keep import item
delete import item
keep function definition

+filter-function-def-delete delete function definition

keep module definition
delete module definition
keep package definition

+filter-package-def-delete delete package definition

keep port definition
delete port definition
keep defparam statement
delete defparam statement
keep path statement
delete path statement
keep event trigger
delete event trigger
keep procedural assignment
delete procedural assignment
keep deassign statement
delete deassign statement
keep disable statement
delete disable statement
keep attribute specification
delete attribute specification
keep structural if statement
delete structural if statement
keep structural for statement
delete structural for statement
keep structural case statement
delete structural case statement
keep udp table
delete udp table
keep enum specification
delete enum specification
keep member reference (structure, class or external
delete member reference (structure, class or external
keep return
delete return
keep preincrement
delete preincrement
keep postincrement
delete postincrement
keep predecrement
delete predecrement
keep postdecrement
delete postdecrement
keep data type change
delete data type change

+filter-assignment-pattern-keep keep assignment_pattern

+filter-assignment-pattern-delete delete assignment_pattern

keep queue dimension
delete queue dimension

* 'rectify' Options

+rectify-default-value={0|1} change default replacement value

+rectify-attribute-name=<attrName> attribute name used to override default replacement value

+rectify-delete-decl-pragmas delete pragmas attached to declarations

* 'sim' Options

start simulation in interactive mode only
do not simulate, compile only
enable execution tracing
use minimum delays
use typical delays
use maximum delays

+sim-pli=pliLib1+pliLib2+... load pli librarys

use file for logging
use file for key stroke log

* 'xprop' Options

insertion begin pragma
insertion end pragma
insertion clock begin pragma
insertion clock end pragma
disable task output instrumentation
disable if instrumentation
disable case instrumentation
disable reference instrumentation
disable '?' instrumentation
attribute specifing variable will never be x
declare integers will never be x
instrument register clocks

+xprop-clk-edge-control=[!]<tickdefine> Supply a preprocessor tick define to enable instrumentation on both edges of the clock. ! indicates tickdefine disables both edges. If switch isn't supplied the behavior is single edge unless XPROP_BOTH_EDGES is defined


Written by Mark Hummel

Reporting Bugs

Report bugs at <http://sourceforge.net/projects/vrq>


Vrq 1.0.124 August 2016