vpassert man page
vpassert — Preprocess Verilog code assertions
vpassert [ --help ] [ --date ] [ --quiet ] [ -y directories... ] [ files... ]
Vpassert will read the specified Verilog files and preprocess special PLI assertions. The files are written to the directory named .vpassert unless another name is given with -o. If a directory is passed, all files in that directory will be preprocessed.
Standard VCS and GCC-like parameters are used to specify the files to be preprocessed:
+libext+I<ext>+I<ext>... Specify extensions to be processed -f I<file> Parse parameters in file -v I<file> Parse the library file (I<file>) -y I<dir> Parse all files in the directory (I<dir>) -II<dir> Parse all files in the directory (I<dir>) +incdir+I<dir> Parse all files in the directory (I<dir>)
To prevent recursion and allow reuse of the input.vc being passed to the simulator, if the output directory is requested to be preprocessed, that directory is simply ignored.
Preprocess and write out files that do not have any macros that need expanding. By default, files that do not need processing are not written out.
This option may speed up simulator compile times; the file will always be found in the preprocessed directory, saving the compiler from having to search a large number of -v directories to find it.
Special Axiom ATHDL enables/disables added around unreachable code.
- --call-error <function>
$uassertetc.) wants to display a message, call the specified function instead of
- --call-info <function>
$uinfowants to display a message, call the specified function instead of
- --call-warn <function>
$uwarn_clketc.) wants to display a message, call the specified function instead of
Check file dates and sizes versus the last run of vpassert and don't process if the given source file has not changed.
Exclude processing any files which begin with the specified prefix.
Displays this message and program version and exits.
- --language <1364-1995|1364-2001|1364-2005|1800-2005|1800-2009|1800-2012|1800-2017>
Set the language standard for the files. This determines which tokens are signals versus keywords, such as the ever-common "do" (data-out signal, versus a do-while loop keyword).
Include `__message_minimum in the
$uinfotest, so that by defining __message_minimum=1 some uinfos may be optimized away at compile time.
Do not emit `line directives. If not specified they will be used under --language 1364-2001 and later.
Delete all 'simple' PLI calls. PLI function calls inside parenthesis will not be changed, and thus may still need to be manually ifdef'ed out. Useful for reducing the amount of `ifdef's required to feed non-PLI competent synthesis programs.
$stopstatement. With --nostop, this is replaced by incrementing a variable, which may then be used to conditionally halt simulation.
- --o file
Use the given filename for output instead of the input name .vpassert. If the name ends in a / it is used as a output directory with the default name.
Suppress messages about what files are being preprocessed.
Special RealIntent enable/disables added around unreachable code.
When "ifdef SYNTHESIS" is seen, disable coverage. Resume on the `else or `endif. This does NOT follow child defines, for example:
`ifdef SYNTHSIS `define MYSYNTH `endif `ifdef MYSYNTH // This will not be coveraged-off
- --timeformat-units units
If specified, include Verilog
$timeformatcalls before all messages. Use the provided argument as the units. Units is in powers of 10, so -9 indicates to use nanoseconds.
- --timeformat-precision prec
When using --timeformat-units, use this as the precision value, the number of digits after the decimal point. Defaults to zero.
Special Vericov enable/disables added around unreachable code.
Special Verilator translations enabled.
Displays program version and exits.
Special Synopsys VCS enables/disables added around unreachable code.
These Verilog pseudo-pli calls are expanded:
Disable coverage for all tools starting at this point. Does not need to be on a unique line.
Re-enable coverage after a vp_coverage_off. Does not need to be on a unique line.
- $uassert (case, "message", [vars...] )
$uerrorif the given case is FALSE. (Like assert() in C.)
- $uassert_amone (sig, [sig...], "message", [vars...] )
$uerrorif more than one signal is asserted, or any are X. (None asserted is ok.) The error message will include a binary display of the signal values.
- $uassert_info (case, "message", [vars...] )
$uinfoif the given case is FALSE. (Like assert() in C.)
- $uassert_onehot (sig, [sig...], "message", [vars...] )
$uerrorif other than one signal is asserted, or any are X. The error message will include a binary display of the signal values.
- $uassert_req_ack (req_sig, ack_sig, [data_sig,...] )
Check for a single cycle request pulse, followed by a single cycle acknowledgment pulse. Do not allow any of the data signals to change between the request and acknowledgement.
- $ucheck_ilevel (level )
Return true if the __message level is greater or equal to the given level, and that global messages are turned on.
- $ucover_clk (clock, label)
$uerror_clk, add a SystemVerilog assertion at the next specified clock's edge, with the label specified. This allows cover properties to be specified "inline" with normal RTL code.
- $ucover_foreach_clk (clock, label, "msb:lsb", (... $ui ...))
$ucover_clk, however cover a range where
$uiin the expression is replaced with the range index.
Range is "msb:lsb" to indicate from msb downto lsb inclusive, and/or a comma separated list of values.
for ($ui=msb; $ui>=lsb; $ui=$ui-1) begin if (expression with $ui) $ucover_clk(clock, label ## "_" ## bit) end
However there's no way to form a label from a for loop (as psudocoded with ## above), thus this macro.
Loop index used inside
- $uinfo (level, "message", [vars...] )
Report a informational message in standard form. End test if warning limit exceeded.
- $uerror ("message", [vars...] )
Report a error message in standard form. End test if error limit exceeded.
- $uerror_clk (clock, "message", [vars...] )
Report a error message in standard form at the next clock edge. If you place a
$uerroretc in a combo logic block (always @*), event based simulators may misfire the assertion due to glitches.
$uerror_clkfixes this by instead creating a temporary signal and then moving the assert itself to a new clocked block at the specified edge. Note any variables printed will be the values at the time of the next clock edge, which may differ from the value where the
- $uwarn ("message", [vars...] )
Report a warning message in standard form.
- $uwarn_clk (clock "message", [vars...] )
Report a warning message in standard form at the next clock edge. See
Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA software tool suite. The latest version is available from CPAN and from <http://www.veripool.org/verilog-perl>.
Copyright 2000-2018 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
Wilson Snyder <email@example.com>, Duane Galbi <firstname.lastname@example.org>
Verilog-Perl, Verilog::Parser, Verilog::Pli