llc-7.0 man page
llc — LLVM static compiler
llc [options] [filename]
The llc command compiles LLVM source inputs into assembly language for a specified architecture. The assembly language output can then be passed through a native assembler and linker to generate a native executable.
The choice of architecture for the output assembly code is automatically determined from the input file, unless the -march option is used to override the default.
If filename is "-" or omitted, llc reads from standard input. Otherwise, it will from filename. Inputs can be in either the LLVM assembly language format (.ll) or the LLVM bitcode format (.bc).
If the -o option is omitted, then llc will send its output to standard output if the input is from standard input. If the -o option specifies "-", then the output will also be sent to standard output.
If no -o option is specified and an input file other than "-" is specified, then llc creates the output filename by taking the input filename, removing any existing .bc extension, and adding a .s suffix.
Other llc options are described below.
Print a summary of command line options.
Generate code at different optimization levels. These correspond to the -O0, -O1, -O2, and -O3 optimization levels used by clang.
- -mtriple=<target triple>
Override the target triple specified in the input file with the specified string.
Specify the architecture for which to generate assembly, overriding the target encoded in the input file. See the output of llc -help for a list of valid architectures. By default this is inferred from the target triple or autodetected to the current architecture.
Specify a specific chip in the current architecture to generate code for. By default this is inferred from the target triple and autodetected to the current architecture. For a list of available CPUs, use:
llvm-as < /dev/null | llc -march=xyz -mcpu=help
- -filetype=<output file type>
Specify what kind of output llc should generated. Options are: asm for textual assembly ( '.s'), obj for native object files ('.o') and null for not emitting anything (for performance testing).
Note that not all targets support all options.
Override or control specific attributes of the target, such as whether SIMD operations are enabled or not. The default set of attributes is set by the current CPU. For a list of available attributes, use:
llvm-as < /dev/null | llc -march=xyz -mattr=help
Disable frame pointer elimination optimization.
Disable optimizations that may produce excess precision for floating point. Note that this option can dramatically slow down code on some systems (e.g. X86).
Enable optimizations that assume no Inf values.
Enable optimizations that assume no NAN values.
Enable optimizations that make unsafe assumptions about IEEE math (e.g. that addition is associative) or may not work for all input ranges. These optimizations allow the code generator to make use of some instructions which would otherwise not be usable (such as fsin on X86).
Print statistics recorded by code-generation passes.
Record the amount of time needed for each pass and print a report to standard error.
Dynamically load dso_path (a path to a dynamically shared object) that implements an LLVM target. This will permit the target name to be used with the -march option so that code can be generated for that target.
Specify which EABI version should conform to. Valid EABI versions are gnu, 4 and 5. Default value (default) depends on the triple.
Emit the .stack_sizes section which contains stack size metadata. The section contains an array of pairs of function symbol values (pointer size) and stack sizes (unsigned LEB128). The stack size values only include the space allocated in the function prologue. Functions with dynamic stack allocations are not included.
Print generated machine code between compilation phases (useful for debugging).
Specify the register allocator to use. Valid register allocators are:
Basic register allocator.
Fast register allocator. It is the default for unoptimized code.
Greedy register allocator. It is the default for optimized code.
Register allocator based on 'Partitioned Boolean Quadratic Programming'.
Specify the spiller to use for register allocators that support it. Currently this option is used only by the linear scan register allocator. The default spiller is local. Valid spillers are:
Intel IA-32-specific Options
Specify whether to emit assembly code in AT&T syntax (the default) or Intel syntax.
If llc succeeds, it will exit with 0. Otherwise, if an error occurs, it will exit with a non-zero value.
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